Test Power Optimization with Reordering of Genetic Test Vectors for Vlsi Circuits

Power optimization is one of the important challenges in VLSI circuit for testing engineers. Larger power dissipation becomes the reason for overheating and with every increase in 10oC in operating temperature, failure rates for the component on a chip doubles. Power dissipation is directly proportional to switching activities of the components on Integrated Circuits. Power optimization is possible only by minimizing the toggling count (switching activity) for combinational and sequential components on a chip area. This paper describes novel technique of power optimization by rearranging the test patterns generated by Genetic Algorithm. The logic discussed here calculates and re-arrange these genetic test patterns according to minimum toggling arrangement of test patterns. This algorithm is applied on the ISCAS85 and ISCAS89 benchmark circuits. The experimental results show that maximum power dissipation in the combinational and sequential logic circuits are reduced by the average of 31% and 36% respectively.